Many modern integrated circuits are of the synchronous type, such that their internal operation is governed by an external clock signal. Examples of high density, high speed clocked logic circuits include microprocessors, microcomputers, math co-processors and the like; of course, other simpler circuits such as memories and smaller scale logic circuits may also be governed by external clock signals. Clock signals may be generated in systems using these circuits by way of a stand-alone crystal oscillator circuit, or by connection of a crystal to terminals of the clocked logic device itself in the case where the oscillator is integrated onto the same integrated circuit chip with the logic function.
As is well known in the art, the rate at which a clocked integrated circuit performs its function is generally highly dependent upon the frequency of the clock signal. Especially in digital circuits, this is because the internal chip functions are either directly or indirectly (via frequency dividers, phase-locked loops and the like) controlled by the received clock signal. As such, for the example of a microprocessor, the number of instructions performable by the circuit in a given period of time will vary with the frequency of the clock signal.
Particularly in complex clocked circuits such as microprocessors and math co-processors, the performance of certain circuit functions may depend on the clock frequency while the rate at which other functions are performed may be limited by other factors. For example, certain input/output functions may be limited by bus interface specifications rather than the clock frequency, while the speed of core or CPU functions will likely depend directly on the clock frequency. It is therefore beneficial in such circuits to provide high frequency clocks to certain portions of the circuit (e.g., the CPU or core of a microprocessor), with lower frequency clocks being provided to other portions (e.g., the bus interface). In the field of microprocessors, this desired result is generally referred to as "clock doubling", particularly in the case where the core clock is operating at twice the rate of the bus interface clocks.
A conventional circuit for deriving clock signals at various frequencies from an input clock signal is the combination of a phase-locked loop (PLL) and one or more frequency dividers. In this arrangement, the PLL provides stability in the generated output clock signals relative to the input clock, while the ratio of the frequency dividers in the output and feedback loops determines the relative frequency between the output clock signals and the input clock. However, a PLL circuit cannot instantaneously respond to a change in the input clock frequency, as several transition cycles may be necessary to lock onto a new input clock signal frequency. The ability to rapidly change the internal operating frequency has become important in recent years with the advent of "turbo" mode personal computers and workstations, in which a faster clock rate (e.g., 20 MHz instead of 8 MHz) is enabled by the user via a hardware switch. The transient cycles required for PLL circuits to lock onto a new frequency thus can cause erroneous system operation when turbo mode is selected or deselected.
In addition, PLL-based circuits are generally limited in operating power supply voltage range (primarily due to the operation of the voltage controlled oscillator), and as such are not well-suited for use in circuits that are to operate over a wide power supply voltage range. As modern fabrication technology continues to reduce physical feature sizes such as transistor channel lengths to well below one micron, it is contemplated the use of lower power supply voltages (e.g., 3.3 volts) will become more prevalent in order to avoid reliability problems, such as the hot electron effect. It will therefore become increasingly important for large scale integrated circuits to be able to operate at lower power supply voltages, and perhaps over a range including both the conventional 5 volt power supply voltage and the lower 3.3 volt power supply voltage.
Another known technique for providing different clock frequencies to different circuit portions is to have two terminals for receiving input clocks at different frequencies. In this technique, for example as used in the Intel 80387 math co-processor, the state of another terminal (either hardwired externally or connected in the wiring of an on-chip bond pad) selects whether the clock signal received at the alternate clock terminal is to be ignored or used.
Certain other clock doubling schemes have considered the use of internal frequency dividers to divide down the input clock frequency prior to application to slower circuit functions. For example, it is known to use a half-frequency clock (relative to the input clock frequency) to control the bus interface of a microprocessor circuit. In such arrangements, the frequency divider not only reduces the clock frequency, but also corrects for variations in duty cycle and ringing conditions on the input clock signal. While such correction for input clock instabilities may be performed prior to use in slower circuit functions, these instabilities preclude the direct use of the input clock signal for the high speed circuit functions in the CPU or core. In particular, certain phases of the input clock signal may be too short (especially when unstable) to allow for completion of certain internal core functions.
Furthermore, in the art of internal clock distribution for integrated circuits such as microprocessors and the like, the optimization of duty cycle for internal clocks generated from externally received clock signals has heretofore generally been quite difficult. This is due to the constraints presented by the expected variations of the duty cycle of the external clock, as indicated in various timing specifications; furthermore, as microprocessor clock frequencies increase to 25 MHz and beyond, external clock signals are more susceptible to ringing and other noise effects that increase with faster switching times, resulting in less well defined and controlled clock phases. As such, the generation of internal clock signals from an external clock signal, particularly for high frequency operation, has heretofore required the designer to make tradeoffs in selecting the duration of each phase in the internal clock signals.
It is therefore an object of the present invention to provide an internal clock generation scheme which generates high speed internal clocks at steady duty cycles and lower speed clocks for lower speed circuit functions.
It is a further object of the present invention to provide such a scheme in which the duty cycle of the high speed clock is optimized for the worst case clock phase operation of the integrated circuit.
It is a further object of the present invention to provide such a scheme in which the duty cycle of the high speed clock may be characterized and easily adjusted.
It is a further object of the present invention to provide such a scheme which has a high degree of power supply voltage stability, enabling low voltage operation of the circuit.
It is a further object of the present invention to provide such a scheme in which the generation of the clock may be switched between a clock doubling mode and a non-clock doubling mode.
It is a further object of the present invention to provide such a scheme in which the mode selection may be readily made during the manufacturing process.
Other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.